at Marvell Semiconductor in Boise, Idaho, United States
- Work closely with customer and Marvell design teams to plan and execute the physical placement and routing of the electronic circuits in the design
- Perform Chip planning, I/O planning, global signal planning and hard IP integration.
- Partition the design into multiple blocks and size/shape them.
- Complete block and top floorplanning, macro placement, and pin placement.
- Place and route using industry standard tools.
- Perform clock tree synthesis and optimization.
- Close post route timing